In a gate insulating film of recently semiconductor devices, e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET), an oxynitride film is employed to prevent a so-called pass-through phenomenon. It is often the case that formation of the oxynitride film is performed by subjecting an oxide film to a plasma nitriding treatment.
Meanwhile, it is a recent trend that the MOSFET itself becomes extremely miniaturized and, in concert with such miniaturization, the gate insulating film is controlled to be in an ultra-thin film region (of about 1.0 nm). In such a thin insulating film, however, there is a fear of degradation of a transistor-on current and reduction of an operating speed.
In view of this, JP2004-48001A proposes a method of performing an annealing treatment to an insulating film subsequent to a plasma nitriding treatment thereof in an effort to recover damage caused at the time of plasma nitriding treatment.
However, the conventional annealing treatment is what is called a “heavy annealing treatment”, for the reason of which oxygen is diffused to an interface by the annealing treatment, thereby increasing a thickness of the insulating film and decreasing an operating speed. In particular, there is a concern of degradation of an NBTI (Negative Bias Temperature Instability) characteristic remarkably appearing in a PMOSFET.
As one example of the annealing treatment, there is known an RTP (Rapid Thermal Processing). Although annealing is performed for the purpose of re-sequence impurities or recovering crystal damage after ions are injected into, e.g., a semiconductor wafer (hereinafter often referred to as “wafer”), there is a tendency that, if a thermal budget (thermal treatment quantity) grows high in the annealing process, diffusion of a dopant occurs in a source-drain region of, e.g., a transistor, to thereby create a deep junction. Inasmuch as a shallow junction is indispensable under a miniaturized design rule, use has been made of the RTP capable of reducing a total thermal budget by rapidly raising and lowering a temperature within a short period of time (so-called spike annealing).
It is important in the RTP that an in-plane temperature of the wafer is kept uniform in order to equalize the characteristics of electronic devices manufactured from one and the same wafer. However, if the temperature is straightly and rapidly raised up to a predetermined annealing temperature in the RTP, overshoot occurs in the wafer temperature, thus reducing temperature control accuracy. Furthermore, there is a problem in that non-uniformity in a wafer in-plane temperature becomes great due to the rapid temperature elevation and a crystal defect called “slip” arises as the wafer is warped.
Taking this into account, JP2000-331949A suggests a method for assuring an in -plane temperature uniformity in an RIP, the method being adapted to provide a heat-up process of multiple steps and perform an annealing treatment, while gradually ducing a temperature elevation speed in the respective heat-up steps, until the temperature reaches a predetermined annealing te perature. However, JP2000-331949A provides no concrete and positive disclosure on a temperature region and time in the respective heat-up steps, mean that the method fails to disclose a relationship between a slip and a time/temperature or throughput. Furthermore, although the prior art method can improve overshoot of the wafer temperature and non-uniformity of the in-plane temperature by gradually reduces a temperature elevation speed in the respective heat-up steps, it suffers from a problem of throughput reduction. Considering that a greatest advantage of the RTP resides in its ability to increase a throughput and suppress a thermal budget, the method taught in JP2000-331949A is not satisfactory.